This invention relates to a semiconductor integrated circuit and a method and system for designing a layout of the same.
In conventional layout design methods of a semiconductor integrated circuit (for example, an LSI), the existing design properties are utilized to reduce the number of the design processes for the LSI. As, for example, described in "Handbook of Integrated Circuit Applications", published Jun. 30, 1981 by Asakura Bookstore, edited by Takuo Sugano, pp. 42 to 43, there has been employed as an example of the conventional methods the layout design method generally called the building block method which is presently shown in FIG. 21. According to this method, various different master cells 107 which are previously designed, i.e. designed in advance, and stored in a library are taken out, arranged on a chip 103 and interconnected by wiring lines in a wiring region 108, as shown in FIG. 21, so as to realize the function of the semiconductor integrated circuit. (Here, the term "master cell" means a layout of patterns of a circuit which is previously designed, each of such circuits, such as a gate and a flip-flop, is considered as a unit circuit which is repeatedly used in the integrated circuit.)
However, in the conventional master cell 107, its inner layout is standardized, and its signal input/output positions are fixed along one side of the master cell, so that there is no freedom in selection of the signal input/output positions. Therefore, the master cells need to be so arranged that their signal input/output positions face the wiring region 108. Also, in order for the master cells to be interconnected in accordance with a desired logic circuit (or operation), it is necessary to that the wiring region 108 be large enough for wiring the master cells. Thus, it is impossible according to such layout scheme to design a recently developed VLSI in which a large number of gates are incorporated therein at a high density.